Non-volatile memory technology suitable for flash and byte operation application

ABSTRACT

The present invention provides a non-volatile memory cell structure suitable for the flash memory cell and EEPROM cell (electrically erasable programmable read only memory cell) to perform the byte programming and byte erase operations. In the programming operation, a higher negative voltage applied to the drain region, such that the hot hole is generated to induce the hot electron into the floating gate through the tunneling oxide layer in the lateral electrical field. In addition, the gate voltage is around the threshold voltage, which dependent on the integration circuit device design. Furthermore, the non-volatile memory cell utilized the channel Fowler-Nordheim tunneling for erasing operation. In order to perform the byte erasing operation, the drain junction used as an inhibition switch. Thus, the unselected cell in the same word line is inhibited by biasing the drain to ground. Therefore, the word lines of unselected cells are ground.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to a non-volatile memory cell with its operations, and more particularly to a non-volatile memory cell suitable for flash and byte operation application.

2. Description of the Prior Art

Semiconductor based memory devices largely comprises Random Access Memories (RAM) and Read Only Memory (ROM). RAM is referred to as volatile memory, in that when supply voltage is removed, data is destroyed with the passage of time. ROM devices, including Programmable ROM (PROM), Erasable PROM (EPROM), and Electrically EPROM (EEPROM). Numerous EEPROM cells and flash memory cells can be simultaneously erased, and are characterized by a stacked gate structure comprising a floating gate and a control gate.

The conventional P-channel stacked gate flash cell programming operation is utilized the channel hot hole induces the hot electron to put the electron into the floating gate. Furthermore, erasing operation is utilized FN (Fowler-Nordheim) tunneling through the tunneling oxide by FN tunneling to pull out the electron from the floating gate to the substrate. Accordingly, the programming operation is byte operation but the erasing operation is not.

FIG. 1 shows a conventional EEPROM cell 100 in which more than two binary states may be represented by programming cell 100's threshold voltage to one of many predetermined levels. When the EEPROM cell 100 is read, the current level conducted therein is dependent upon the threshold voltage thereof.

EEPROM cell 100 includes a storage transistor 104 and a select transistor 106 that are formed in a P-type substrate 102. N+ diffusion region 108 serves as the source of storage transistor 104. N+ diffusion region 110 serves as the drain of the storage transistor 104 as well as the source for select transistor 106, and N+ diffusion 112 serves as the drain of select transistor 106. A bit line, BL, of an associated memory array (not shown in FIG. 1) is coupled to the drain 112 of select transistor 106. A high impedance resistor 122 is coupled between the drain 112of select transistors 106 and ground potential. Storage transistor 104 has an interpoly dielectric layer 118 between the floating gate 116 and a control gate 120, and a select transistor 106 has a select gate 122. A tunneling window is formed within the tunneling oxide layer 114 of facilitate electron high voltage between floating gate 116 and the drain 110.

Floating gate 116 is charged by applying an erase voltage V_(E) between 16 through 20 volts to the control gate 120 and 16 through 20 volts to the select gate 122 and 0 volt is applied to the bit line, and source region 108 is floating. Electrons tunnel from the drain region 20 to the floating gate 116, thereby increasing the threshold voltage V_(t) of the storage transistor 104.

The EEPROM cell 100 may be programmed by applying a program voltage V_(pp) between 13-20 volts to the bit line and the select gate 122 while the control gate 120 is grounded and the source region 108 is in a high impedance state. The resultant electric field causes electrons to tunneling oxide from the floating gate 116 to the drain region 112, thereby discharging floating gate 1 16 and decreasing the threshold voltage V_(t) of the EEPROM cell 100. The resultant V_(t) of storage transistor 104, and thus the current conducted by the EEPROM cell 100 during a read operation may be controlled by adjusting the program voltage V_(pp).

Erase take place electrically by F-N tunneling of electrons from the floating gate to the source (source erase) ot to the channel (channel erase). During electrical erase, an oxide field on the order of 10 MV/cm is generated across the thin oxide between the floating gate and the n+ source diffusion (or the channel). This is accomplished by the three types erase methods. The extent of cell erasure is controlled by circuitry, and is done algorithmically by using a series of erase and erase verify operation. Each erase pulse is typically 10 ms in length and is followed by a verification of the erased threshold by sensing the cell current.

One of the erase method is grounded gate source erase that is accomplished by biasing the source to a high potential, about 12V, and grounding the control gate and the substrate. The drain node is allowed to float. This causes electrons to tunnel from the floating gate to the source, which discharges or “erase” the floating gate. Under grounded gate source erase conditions, the source bias generates significant band-to-band tunneling current, which is collected in the substrate. Because the source junction is biased near the avalanche regime, there is some multiplication of the band-to-band current. This current acts as a voltage clamp, thereby limiting further increase of the junction voltage because of a voltage drop in the on-chip pass transistors. If the substrate current is sufficiently high, the hot holes that are generated by the breakdown may start to erase the memory cell. The hot hole erase process is difficult to control and is avoided in well-designed memory cell.

Additionally, some holes that are generated by band-to-band tunneling are trapped in the gate oxide. This may lead to erase threshold non-uniformity, speed-up pf erase time with cycling, degradation of charge retention, or speed-up of gate disturb. Balanced against these negative points is the simplicity of the cell structure, which has led to considerable efforts to engineer junction in order to minimize the effects.

Another erase method is negative gate source erase, which is accomplished by biasing the source node at Vcc (5V) and applying approximately −10V to the control gate. A in the grounded gate approach, electrons tunnel from the floating gate to the source diffusion. As a result, the cell is erased. The band-to-band tunneling generated holes, however, are not heated as much as in the grounded gate case because of reduced lateral electric field between the source and the substrate (only 5 V at the source junction). Thus, the adverse effects from holes that are generated from band-to-band tunneling may be reduced. Offsetting the expected improvement in erase performance is the additional circuit complexity that is required for the switching of both positive and negative voltages by the word-line driver circuit.

Typical operation will have floating gate charged positively with respect to ground when eased and charged negatively with respect to ground when programmed. To read memory transistor, control gate is grounded and gate of select transistor is based positively to provide a low resistance path from its drain contact to drain of memory transistor. Drain contact provides connection to metal bit line. Bit line is biased at a modest positive voltage (e.g. 2V) and the common source line is biased at ground. If floating gate is erased, current can flow from bit line to source region. If floating gate programmed, memory transistor is in a non-conducting state and no current flows. The presence or absence of current flow is sensed to determine the state stored by memory transistor.

The oxide in tunnel window is typically about 10 nm thick. To program memory cell, floating gate must be capacitive coupled to a sufficiently positive potential with respect to drain that a field of about 10 MV/cm appears across tunnel oxide. This is accomplished by biasing poly 2 control gate at about 20 V while biasing select gate at a sufficiently high potential that select transistor is conducting with bit line at ground potential. Under these conditions, drain region provides a source of electrons on the cathode side of tunnel oxide. With 10 Mv/cm appearing across tunnel oxide, fowler-Nordheim tunneling occurs and charges floating gate negatively.

To erase memory transistor, the bias across tunnel oxide must be reversed. This is accomplished by applying a high bias to drain of memory transistor while poly 2 control gate biased at ground in order to keep control gate capacitive coupled to a low voltage. The high voltage is applied to drain memory transistor by applying the desired voltage to bit line while gate of select transistor is biased at a potential that is higher than the desired voltage by at least the threshold voltage of select transistor.

SUMMARY OF THE INVENTION

It is one object of the present invention to provide a cell structure, which can compatibly for flash memory cell and EEPROM cell (electrically erasable programmable reads only memory) applications to reduce the die size.

It is another object of the present invention to combine the flash memory cell and EEPROM cell (electrically erasable programmable read only memory) in a cell structure to perform the byte program and byte erase operation.

It is yet object of the present invention to provide a cell structure with a single transistor to perform the byte operation, so as to reduce the process complexity and decrease the cost effectively.

According to aforementioned objects, the present invention provides a non-volatile memory technology structure suitable for the flash memory cell and EEPROM cell (electrically erasable programmable read only memory cell) to perform the byte programming and byte erase operation. The cell structure comprises a gate stack over the substrate and the isolation structure therein. The gate stack comprises a floating gate on the substrate and an interpoly dielectric layer (IPD) between the floating gate and the control gate. The channel region below the field oxide region and the LDD region (lightly drain doped) below the field oxide region within the substrate. The spacer on the sidewall of the gate stack and a source/drain region below the tunneling oxide layer and adjacent to the LDD region.

During the programming operation, a negative voltage applied to the drain region, such that the hot hole is generated to induce the hot electron into the floating gate through the tunneling oxide layer. In addition, the gate voltage is around the threshold voltage V_(t), which dependent on the integration circuit device design.

In addition, the non-volatile memory cell utilized the channel Fowler-Nordheim tunneling for erase operation. In order to perform the byte erase operation, the drain junction used as an inhibition switch. Thus, the unselected cell in the same word line is inhibited by biasing the drain to ground. Therefore, the word lines of unselected cells are ground.

Other objects, advantages and salient features of the invention will become apparent from the following detailed description taken in conjunction with the annexed drawings, which disclosed preferred embodiments of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:

FIG. 1 is a cross-sectional view of EEPROM cell (electrically erasable programmable read only memory cell) utilized programming and erasing operation to one of many levels of threshold voltage using conventional, prior art technique;

FIG. 2 is a cross-sectional view of the non-volatile memory cell structure with one transistor that suitable byte programming and byte erase operations in accordance with a structure disclosed herein;

FIG. 3 is a top view of the non-volatile memory cell array to illustrate the programming operation in accordance with the structure disclosed herein; and

FIG. 4 is a top view of the non-volatile memory cell array to illustrate the erase operation in accordance with the structure disclosed herein.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Some sample embodiments of the invention will now be described in greater detail. Nevertheless, it should be recognized that the present invention can be practiced in a wide range of other embodiments besides those explicitly described, and the scope of the present invention is expressly not limited except as specified in the accompanying claims.

The present invention provides a P-channel non-volatile memory cell that is invented to fit both the byte operation and flash operation in the same chip for the system on chip (SOC) era. Therefore, the present invention provides a flash memory cell only utilized one transistor to perform the byte operation by using P-channel non-volatile memory cell so as to the space of the memory cell can be reduced and the complex process can be simplified, and the cost can be greatly decreased.

Referring to FIG. 2, the present invention provides a flash memory cell 10 with one transistor, which includes a P-type substrate 12 and an N-type well 14 formed therein, wherein the conductivity of the P-type is opposite to the N-type. A P-channel MOS (metal-oxide-semiconductor) stacked gate storage transistor 18 is formed on the P-substrate 12. A drain 24 of P-type conductivity of the P-channel MOS stacked gate storage transistor 18 is formed in the N-type well 14. Similarly, a source 22 of P-type conductivity of the P-channel MOS stacked gate storage transistor 18 is formed in the N-type well 14, which spaced apart from the drain region 24. In additional, the source region 22 is spaced apart by the isolation structure (not shown in FIG. 2) such that the source voltage can be controlled respectively, wherein the isolation structure can be LOCOS (field oxide region) or STI (shallow trench isolation) 14.

The P-channel MOS stacked gate storage transistor 18 has a floating gate 18 a, typically polysilicon, is positioned over the tunneling oxide 16. The floating gate 18 a of the P-channel MOS stacked gate storage transistor 18 is spaced apart from the source region 22. A control gate 18 c is positioned above the floating gate 18 a. In addition, a first insulator layer 16 as the tunneling oxide layer is disposed between the floating gate 18 a and the N-type well 14, and a second insulator layer as an interpoly dielectric (IPD) layer 18 b is disposed between the floating gate 18 a and control gate 18 c, wherein the material of the IPD layer 18 b can be an ONO layer (oxide/nitride/oxide).

In order to perform the byte programming and byte erase operations in the non-volatile memory cell, the preferred embodiment of the present invention provides a cell structure with one transistor to reduce the size of the cell structure and the performance would be enhanced. In addition, the programming operation utilized the channel hot hole to induce the hot electron injection and the erase operation utilized the FN (Fowler-Nordheim) tunneling. Thus, either the programming or erase operations are low voltage and low power consumption.

As shown in FIG. 3, the programming operation for the non-volatile memory with one transistor is similar to the programming operation of the conventional flash memory cell. The non-volatile memory cell is programmed by applying a negative voltage around −4 to −6 volts to the drain region to induce hot electron, wherein the hot electron with high energy, and in the channel near the drain region. The hot electrons accelerate across the tunneling oxide layer and into the floating gate. The hot electrons are into the floating gate, which is surrounded by an insulator layer. A gate is a “floating gate” when it is located between a control gate and the N-type well, and is not connected word line, bit line, or other line. The insulator layer can include the interpoly dielectric layer and the tunneling oxide layer. The floating gate would increase the threshold voltage V_(t) of the non-volatile memory cell. The non-volatile memory cell is programmed by this change in the threshold voltage V_(t) and the channel conductance of the non-volatile memory cell created by the floating gate. The floating gate can hold charge almost indefinitely, even after the power is turned off to the memory cell.

During the programming operation, the negative drain voltage V_(dd) is applied to the drain region and the gate voltage V_(g) is around the threshold voltage V_(t) that dependent on the design, wherein the threshold voltage V_(t) in the preferred embodiment is around −4 volts. Due to the drain voltage V_(dd) is higher than the threshold voltage V_(t) to induce the hot electron injection from channel through the tunneling oxide layer into the floating gate, such that the electrons are hold in the floating gate. Furthermore, the bias would only allow a sub-threshold current flow in the flash cell during the programming operation, such that the injection efficiency is high for this flash cell and the power consumption of the integration circuit device would be lowered.

On the other hand, the word line 0 of the unselected cell devices are applied a threshold voltage V_(t) and word line 1 of the unselected cell devices are grounded (0 volt) in the cell array. The bit line 0 is applied a negative drain voltage V_(dd) and the bit line 1 is grounded.

In addition, in order to avoid the distribution during the programming operation, the word line I is grounded and the voltage of the word line 0 approach the negative threshold voltage, V_(g)=−V_(t), but the bit line 1 is grounded, such that the transistor exhibits turn off state. Because there is no lateral electric field to generate the hot electron, so as to the hot electron is not generated. Thus, there the no programming occurred. Thus, the state of the gate transistor is turn off while the threshold voltage V_(t) is applied to the word line 0 is higher than the drain voltage V_(dd).

Referring to FIG. 4, the preferred embodiment of the present invention provides the flash memory cell is erased by channel Fowler-Nordheim (FN) tunneling. In order to perform the byte erase operation, the erase voltage V_(E) is applied to the bit line 0, and the N-type well and the bit line 1 are grounded, the word line 0 is applied a negation voltage, V_(pp), and the word line 1 is grounded as well as the bit line 1. In addition, the voltages of the source line 0 and source line 1, therefore, the source voltage exhibits floating, and the erase voltage V_(E) is applied to N-well region. The high electrical field from biases of +V_(pp) and −V_(E) would pull the electrons of floating gate to N-type well by F-N tunneling.

For the P-channel flash cell, the control gate voltage V_(CG) is higher (less negative) while the electron hold in the floating gate, in contrast, the control gate voltage V_(CG) is decreased 9more negative) when the electron is pulled out from the floating gate through the tunneling oxide layer into the N-type well.

If the control gate voltage V_(CG) is higher than the threshold voltage V_(t), the P-channel flash transistor would be “turned on” to perform the erasing operation. On the other hand, the channel is increased over the surface of the N-type well when the voltage is applied to the gate to let the PMOS turned on. If the bit line bias is positive VE, the high electrical field electron control gate (−V_(pp)) and channel (+V_(E)) would pull the electron from the floating gate to channel via F-N tunneling through the tunneling oxide. If the bit line bias is grounded, the electrical field between the control gate (−V_(pp) or grounded) and channel (grounded) was not enough to assist FN-tunneling to pull out electron from floating gate. So it would achieve byte erase by selecting the WL and BL bias.

Furthermore, the source lines (source line 0 and source line 1) along the bit line direction is divided by the isolation structure, which comprises the isolation structure to block the leakage current between the different cells on the same word lines. In order to release the constraint of high voltage in the periphery devices, the negative voltage is applied to the gate and the positive voltage is applied to the drain region and n-well region. Thus, the thinner gate oxide and lower V_(BDSS) can be sustained this non-volatile higher operating voltage operation to simply the process and reduce the cost.

According to aforementioned descriptions, the advantages of the present invention as following: firstly, the non-volatile memory cell only utilized one transistor to perform the byte programming operation and the byte erase operation, such that the device area can be diminished to shrink the integration circuit size. It could be served flash and EEPROM applications with one transistor technology.

Secondly, the operating voltage is smaller than the EEPROM or conventional flash memory cell such that the cost and the power consumption can be reduced. It is also simply the fabrication process.

Thirdly, during the erasing operation, the channel potential is depended on the state of the bit line to let the electric field of the transistor is not enough to perform the erasing operation to pull down to the N-type well from the floating gate, or inhibit the erase to reduce the electrical field.

Although specific embodiments have been illustrated and described, it will be obvious to those skilled in the art that various modifications may be made without departing from what is intended to be limited solely by the appended claims. 

1. A non-volatile memory cell structure, said structure comprising: an N-type well region in a substrate, a channel region between a P-type source region and a P-type drain region, wherein the conductivity type of said P-type is opposite to said N-type; a first insulator layer on the surface of said N-type well region; a floating gate overlying said first insulator layer; a second insulator layer on said floating gate; and a control gate on said second insulator layer, wherein said non-volatile memory cell is erased by applying an erase voltage to said P-type drain region, applying a supply voltage to said control gate, and said erase voltage applied to said N-type well region.
 2. The structure according to claim 1, wherein said erase voltage between about 12 volts.
 3. The structure according to claim 1, further comprising a source line coupled to said P-type source region, said source line exhibits floating.
 4. The structure according to claim 3, wherein said source line is divided by an isolation structure along a bit line direction.
 5. A semiconductor memory cell structure, said structure comprising: an N-type well region in a substrate, a channel region between a P-type drain region and a P-type source region, wherein the conductivity type of said N-type is opposite to said P-type; a insulator layer overlying said N-type well region; and a gate transistor on said insulator layer, said gate transistor comprises a control gate coupled to a word line, said P-type drain region coupled to a bit line, wherein said cell is erased by applying an erase voltage between about 12 volts to said P-type drain region, and applying a supply voltage to said control gate.
 6. The structure according to claim 5, wherein said P-type source region coupled to a source line.
 7. The structure according to claim 6, wherein said source line is divided along a bit direction by using an isolation structure.
 8. The structure according to claim 5, wherein a supply voltage applied to said N-type well region is erase voltage.
 9. The structure according to claim 5, wherein said cell is programmed by applying a negative supply voltage between 6-10 to said P-type drain region to induce hot electron, and a negative threshold voltage is of about 2 volts applied to said word line.
 10. A method for erasing non-volatile memory cell having a P-type substrate and an N-type well region therein, a channel region between a P-type drain region and a P-type source region, said method comprising the steps of: applying an erase voltage to said P-type drain region to cause tunneling of electrons from a floating to said N-type well region and to said N-type well region, wherein said P-type drain region coupled to a bit line; applying a supply voltage to a control gate, wherein said control gate coupled to a word line; and grounding said word line of unselected cell and said bit line of unselected cell to cause the P-type drain region as an inhibit switch.
 11. The method according to claim 10, wherein said erase voltage is of about 12 volts. 